1. Field of the Invention
The present invention relates to multiple processors in computer systems and more particularly to multiple processors having a common reset using a single ROM.
2. Description of the Prior Art
The personal computer industry is a vibrant and growing field that continues to evolve as new innovations occur. The driving force behind this innovation has been the increasing demand for faster and more powerful personal computers. New and increasingly more complex applications for personal computers are continually being developed, and the computer programs required to implement these new applications have experienced a corresponding increase in size and complexity, requiring greater amounts of time for the computer to be able to run them properly. As a result, personal computers have been burdened with lengthier amounts of software instructions that take increasing amounts of time for them to execute.
To meet the challenge of these new software applications, computer designers have used various methods to increase the speed with which personal computers can process instructions. Historically, the personal computer has developed as a system utilizing a single microprocessor to handle all instruction execution. The microprocessor is the key working unit or "brains" of the personal computer, and its task is to handle all of the instructions that programs give it in the form of computer software. The methods that have been used to increase speed in the personal computer have generally centered around maximizing the efficiency with which this single microprocessor can handle instructions.
Limits are being reached, however, on the amount of speed that can be obtained from a system based on a single microprocessor. The obvious choice to remove this constraint has been the incorporation of multiple microprocessors operating in parallel into a computer system. With the use of multiple processors, or multiprocessing, each microprocessor can be working on a different task at the same time. The use of multiprocessing has generally increased computer performance, but it has also resulted in numerous difficulties that were not found in a single processor environment.
A problem that has arisen in multiprocessing has been how to start up 6r initialize each of the processors without them interfering with each other. In a single processor personal computer environment, the microprocessor generally initializes itself by performing a POST (power on self test). The POST program is located in the computer's ROM, which is a special type of memory that is permanently recorded into the computer. This special memory cannot be written to or changed by software and is nonvolatile, meaning that turning off the computer will not disturb it. The ROM holds a key set of programs that provide essential support for the operation of the computer, among these the test and initialization programs known as the POST, which make sure that the computer is in good working order at power on. The POST program usually includes the microprocessor placing the memory in a known state, testing any memory, placing peripherals in a tested, reset and ready condition and loading or booting up the operating system, among other things.
The problem that arises in multiprocessing is that, in a system where multiple processors coexist sharing a common bus and a common memory, it would be catastrophic for more than one processor to perform a complete POST. For example, if one processor had completed a POST and was up and running, a subsequent processor attempting to perform a POST would re-initialize the peripherals and memory that the previous processor was now using to run its code, resulting in a potential error for the first processor.
For this reason it would seem necessary in a multiprocessing environment for each processor to have its own ROM with which to bring itself to a working state so that one processor's initialization would not interfere with another processor that may already be up and running. However, this scheme would require that numerous ROM's be present in the computer, one associated with each processor, resulting in an unnecessarily large amount of nonvolatile memory being used for this purpose. A further problem that would be associated with the use of multiple ROM's would be the resultant complexity and loading effects on the bus that these ROM's share with the processor. Therefore, it would be highly desirable for these multiple processors to be able to start or "boot" up using a single, common ROM as opposed to each processor containing a different ROM in memory.
For further background on the present invention, it is necessary to examine some of the special features and considerations involving the Intel Corporation (Intel) family of microprocessors, which are used in personal computers compatible with those manufactured and sold by International Business Machines Corp. (IBM). The Intel 80286 microprocessor introduced a new feature that allowed it to operate in two different modes: real mode and protected mode. In real mode, the 80286 behaves very much like the 8088 microprocessor that was in the original IBM PC, thus allowing for full compatibility with these older systems. In protected mode, there are no compatibility considerations, and the 80286 is allowed to utilize all of its special features for maximum capability.
A problem soon became apparent, however, in that, while provisions were made for the 80286 microprocessor to switch from real to protected mode, no provisions were made for the 80286 to return from protected to real mode. This problem was corrected in the Intel 80386 microprocessor, but could only be remedied in the 80286 through the use of the reset operation to return the processor to real mode. The reset operation, however, generally required the computer to perform a complete reset and reboot, and this was found to be unnecessary for the purpose of simply returning the computer from protected to real mode. Therefore, it was determined that some method was needed to indicate whether each reset operation was simply a software reset used for protected to real mode switching or a true system reset, and, as a result, a byte was provided in the CMOS nonvolatile memory available in the computer system to reflect whether or not a full reboot of the system was necessary. At power on, this byte reflects a "normal POST" status, informing the processor that a protected mode reset is not occurring and that a full boot is necessary to begin operation. When the processor is up and running, the status of this byte is changed to reflect a "vector on reset" status when a protected to real mode change is desired, thus informing the processor that a complete reboot is unnecessary.
The processor generally polls the status of this reset byte during its POST program so that the protected to real mode switch can be made with a minimum of lost time. At power on, the normal POST boot status of the reset byte directs the microprocessor to perform a complete POST, whereas, when the processor has been up and running and has its RESET pin toggled, the vector on reset status of the reset byte directs the processor away from the remainder of the POST program to an alternate memory location which is contained in a reset vector location. This memory location is the location desired upon entry into real mode to continue operation of the computer.